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Epitaxial Wafers

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Wafer Works also provides high-quality 4" - 8" epitaxial wafers and buried layer epitaxial process services, meeting customer's power device and CMOS demands and offering one stop-shopping services.

Specifications of Silicon Epi-Substrate

Service type	Diameter (mm)	Epitaxial Thickness (μm)	Resistivity Range (ohm．cm)
Silicon Epitaxial Wafer	100/125/150/200	2.00~150	0.05~60
Buried EPI Service	150/200	2.00~20	0.10~50

	01	Crystal Growth We use the Czochralski (CZ) method to grow both p-type and n-type dislocation-free silicon ingots with <100>, <111> or <100> orientation. The diameters of the ingots are 100mm, 125mm, 150mm, and 200mm. The dopant types used, and the matching resistivity ranges for each dopant are listed in the product tables. For the p-type boron doped ingots, the lowest resistivity that can be obtained for an ingot is 0.0006 ohm．cm. For an n-type ingot, the lowest resistivity obtained by doping with red-phosphorus is 0.0011 ohm．cm. To ensure high gettering ability and mechanical strength, the oxygen contents of the ingots are regulated. We also pay special attention to improve radial uniformity and to minimize the as-grown defects, such as COP, swirl and dislocation loops in an ingot.
	02	Slicing Slicing follows the process of cutting the ingot into thin wafer slices. Wafer Works used cutting-edge wire and I.D. saws that are operated by experienced and well-trained operators to produce high quality wafers. The techniques with low kerf loss are applied to achieve thin wafers and help to ensure wafer flatness, and total thickness variation (TTV) is controlled to minimum.
	03	Edge Grinding After slicing process, edge grinding technology is used to create rounded edges on each wafer. The purpose of this step is to minimize edge chipping, breakage and thermal induced slip in the subsequent customer's thermal processes. For different Epi thickness and/or processes, an optimized edge profile and length can be precisely processed to fulfill customer's specifications.
	04	Lapping Lapping is the process to remove residual slicing damages on the wafer surface. Initial refinement on wafer flatness is also finished during this process.
	05	Etching Both acid and caustic etching are available for various customer's requirements. The damaged layers caused by the previous processes are removed during etching process. We can also provide a residual damage layer during the caustic etching process for backside gettering purposes. Special shape control can be achieved with state-of-the-art etching machines and techniques.
	06	Backside Treatment To satisfy customer's detailed requirements, Wafer Works is capable of adding LTO, poly-back, or backside damage (BSD) to the backside of wafers. These treatments help to ensure high device yield. For thick poly-back, Wafer Works has developed a unique patented process to ensure wafer flatness.
	07	Polishing Polishing techniques have a tremendous impact on the outcome of the wafer surface. Sophisticated polishing process has been used to produce world-class silicon wafers in Wafer Works.
	08	Cleaning The cleaning process removes surface metals and micro particles from wafer surface. An effective final cleaning process has been developed in Wafer Works to ensure the clean lines of output wafer products.
	09	Epitaxy Epitaxy is a CVD (Chemical Vapor Deposition) proces, a single layer (or multiple layers) of mono-crystalline Si is grown on the surface of a single crystal substrate. Since the characteristics of the epitaxial surface are superior to those of the polished Si substrate, it is more suitable for dence process. Our Epitaxial process utilizes state-of-the-art equipment with cutting-edge technologies.
	10	Visual Inspection In order to supply defect-free products to our customers, we have conducted visual inspection on each wafer in the dark room with the assistance of the auxiliary light sources.
	11	Wafer Characterization After the wafer has undergone polishing and cleaning processes, advanced equipment and cutting-edge technology are used to accurately measure the wafer's resistivity, thickness, TTV, STIR, bow and warp, etc. to fulfill customer's requirements.
	12	Wafer Clearance Inspection To ensure high quality wafers will be delivered to customers, state-of-the-art surface inspection equipments are used to accurately measure particle count on the wafer surface for final screening before packaging.
	13	Package The wafers are desiccated with a nitrogen purge to evacuate humidity down lower <10%, tape sealed, double bagged (PE + Aluminum Bag), and then vacuum packed in a class 10 clean room environment.